In order to catch up with a fast increasing multimedia function, system on chip SoC technique in which millions of gates are embodied on one chip is necessary. The SoC is a semiconductor integration circuit in which main functions of the system are integrated on one chip. The SoC includes all hardware and software functions needed for a system, such as a memory, a processor, an external interface, analog and hybrid mode block, built-in software, an OS and so forth.
The SoC has an interconnection structure in which all components share one bus for intercommunication. However, there is a disadvantage of slow communication speed between the components. In addition, since signals are transferred to not only designated component but all components, high power consumption problem arises. Moreover, although 8 to 10 components are mounted on one chip currently, a structure of a chip should be extended enough to employ about 50 to 100 components in the near future. In this case, the more the number of connected components are, the more a load is. As a result, a transmission speed between components becomes slow. Resultantly, it is impossible to unlimitedly increase the number of the component included in one chip using a bus structure.
Like this, the bus structure has been adopted for an interconnection between the components in the present SoC. However, there are many problems such as non-scalability, long arbitration delay, and limited bandwidth, leading to the bottleneck phenomenon. In addition, since a plurality of bus masters compete to obtain a control capacity of the bus, a data transmission delay is increased as the number of the bus master is increased. Because the performance of the bus is determined by the IP, the performance of bus is cannot be used maximally. Also, a switching using the present bus structure is embodied in a synchronous system, so that a clock is necessary and other problems arise therefrom.
In the meanwhile, a network on chip has been investigated in order to solve above-mentioned system on chip structure and support smooth communication between a large number of IPs in one chip. If the network on chip is applied, it is expected to be possible to solve several problems such as limitation of scalability, long arbitration delay, power consumption and so forth. However, still many investigations are requested to do so.